’˜ ‘ / Books
1. u”Œ“±‘ÌŒ€‹†4ŠªFƒGƒsƒ^ƒLƒVƒƒƒ‹¬’·v,ŒàVˆê•ÒAŒFìªŽ¡AŠp“ì‰p•vAŽ›èŒ’AŒàVˆê‹€’˜,uŒõ‹C‘ŠƒGƒsƒ^ƒLƒVƒƒƒ‹–@v,pp. 1-13(‘æ4‰ñ”Œ“±‘̐ê–åuK‰ï—\e
W) (1969”N3ŒŽ25“ú), (Š”) H‹Æ’²ž‰ïA“Œ‹ž), 1969”NB
"Semiconductor Research #4 : Epitaxial Growth," J. Nishizawa (Ed.) S. Kumagawa, H. Sunami, K. Terasaki, and J. Nishizawa(coauthor) , "Light Assisted Epitaxial Growth," pp. 1-13 Kogyochosa-kai, 1969.
2. u”Œ“±‘ÌŒ€‹†4ŠªFƒGƒsƒ^ƒLƒVƒƒƒ‹¬’·vAŒàVˆê•ÒAŠp“ì‰p•vAŒàVˆê‹€’˜AuƒVƒŠƒRƒ“‚Ì‹C‘Š¬’·‘w‚É‚š‚¯‚éÏ‘wŒ‡Š×‚̍\‘¢vFpp. 15-29A(‘æ4‰ñ”Œ“±‘̐ê–åuK‰ï—\eW)A @(1969”N3ŒŽ25“ú,A(Š”) H‹Æ’²ž‰ïA“Œ‹ž), 1969”NB

"Semiconductor Research #4 :Epitaxial Growth," J. Nishizawa (Ed.), H. Sunami and J. Nishizawa(coauthor), "Stacking Faults in Silicon Epitaxial Layer," pp. 15-29 Kogyochosa-kai, 1969.
3. uMOS LSI»‘¢‹ZpvA(“¿ŽR鰁A‹Ž–{“Nˆê•Ò)AŠp“ì‰p•v‹€’˜A u‘æ1Í:MOS ƒfƒoƒCƒX‚ÌŠî–{“Á«/‘æ2Í:ƒg[ƒ^ƒ‹EƒvƒƒZƒXvA pp. 11-48A“úŒoƒ}ƒOƒƒqƒ‹ŽÐA1985”NB

"MOS LSI Fabrication Technologies," T. Tokuyama & N. Hashimoto(Ed.), H. Sunami(co-author), "1. MOS devices & 2. Total process,", pp. 11-48, Nikkei MacGrow Hill, 1985D
4. u”Œ“±‘ÌŒ€‹†24ŠªF’ŽLSI‹Zp, 10’ŽLSI‰ñ˜H‚ƃvƒƒZƒXvA ŒàVˆê•ÒAŠp“ì‰p•vAóˆä²“ñ˜Y‹€’˜Auƒ_ƒCƒiƒ~ƒbƒNMOSƒƒ‚ƒŠ‹ZpvApp.51-79A(‘æ24‰ñ”Œ“±‘̐ê–åuK‰ï—\eW) (1986”N8ŒŽ15“új, (Š”) H‹Æ’²ž‰ïA“Œ‹ž), 1986”NB

"Semiconductor Research #24 : VLSI Circuits and Process," J. Nishizawa (Ed.), H. Sunami & S. Asai (coauthor), "Dynamic MOS Memory Technology," pp. 51-79, Kogyochosa-kai, 1986
5. uƒfƒoƒCƒXÞ—¿HŠwv, (–k“c³O,Œã“¡˜aO•Ò), Šp“ì‰p•v‹€’˜, u‘æ7ÍFWÏ‰ñ˜HÞ—¿‹Zpv, pp. 136-155A ŠC•¶“°A1988”N3ŒŽB
"Device Material Technology," M. Kitada & K. Goto (Ed.), Hideo Sunami (co-author), "7. Integrated Circuit Material Technology," pp. 136-155, Kaibundo, March 1988.
6. uŽŸ¢‘ã’ŽLSIƒvƒƒZƒX‹Zp(Šî‘b•Ò)v, (œA£‘SF•Ò), Šp“ì‰p•v‹€’˜, u‘æ2ß:ƒg[ƒ^ƒ‹@ƒvƒƒZƒXv, pp. 27-39, ƒŠƒAƒ‰ƒCƒYŽÐ, 1988”N4ŒŽ.

"Advanced VLSI Process Technology," Masataka Hirose(Ed.), H. Sunami (coauthor), " 2. Total process," pp. 27-39, Realize Inc., April 1988D
7. uVLSI»‘¢‹Zpv, (“¿ŽR–÷•¢A‹Ž–{“Nˆê•Ò)AŠp“ì‰p•v‹€’˜:u‘æ1Í:MOSƒf@ƒoƒCƒX‚ÌŠî–{“Á«, 2ÍFƒg[ƒ^ƒ‹EƒvƒƒZƒXv, pp. 1-57, “úŒoBPŽÐA“Œ‹žA1989”N1ŒŽB
"VLSI Fabrication Technologies,"T. Tokuyama & N. Hashimoto(Ed.), H. Sunami (co-author), "1. MOS devices & 2. Total process,", pp. 1-57, Nikkei BP, Jan. 1989.
8. uŒŽŠ§Semiconductor World •Êû†v, Šp“ì‰p•v‹€’˜, u‘æ‚PÍFMOSƒvƒƒZƒXƒtƒ[ƒ`ƒ„[ƒg - 16MDRAM‚ð—á‚É‚Æ‚Á‚Ä - v, pp. 35-41, 1989”N11ŒŽ2“ú.

"Supplement to Monthly Semiconductor World,", Hideo Sunami (co-author), "1. MOS process flow chart -16M DRAM-,"pp. 35-41, Semiconductor World, Nov. 2, 1989.
9. uEncyclopedia of Applied Physics, Vol 17v, •Ä‘•š—Šw‰ï, Hideo Sunami‹€’˜, "Semiconductor-Device Integration," pp. 181-198, 1996”N.

"Encyclopedia of Applied Physics," Vol. 17 , AIP, Hideo Sunami(co-author), "Semiconductor-Device Integration," pp. 181-198, 1996.
10. u”Œ“±‘̑厫“Tv,iH‹Æ’²ž‰ï, ›–ì‘ì—Y, ìŒ„ŠÄCj, Šp“ì‰p•v‹€’˜FuŽ©ŒÈ®‡‹Zpv, pp. 622-625, H‹Æ’²ž‰ïC1999”N12ŒŽB

"Dictionary of Semiconductor Technology, Industry,", Kogyochosa-kai, T. Sugano & G. Kawanoishi (Ed.), Hideo Sunami(co-author), "Self-align technology," pp.622-625, Kogyochosa-kai, Dec. 1999.
11. uŽŸ¢‘ãULSIƒvƒƒZƒX‹Zpv, (L£‘SF•Ò), Šp“ì‰p•v‹€’˜Fu‘æ1ÍFŽŸ¢ ‘ãULSI‚Æ‚Í, 2ÍFULSIWÏ‰» ‹Zpv, pp. 3-57, ƒŠƒAƒ‰ƒCƒYŽÐ, 2000”N2ŒŽB

"Advanced ULSI Process Technology," Masataka Hirose(Ed.), H. Sunami (coauthor), "1. Advanced ULSI, 2. Integration process, " pp. 3-57, Realize Inc., February 2000.
12. uƒ}ƒCƒNƒƒGƒŒƒNƒgƒƒjƒNƒX‚É‚š‚¯‚鍂•ªŽqÞ—¿v, (iŽÐj‚•ªŽqŠw‰ï•Ò), Šp“ì‰p•v‹€’˜, u‘æ1Í: ULSI‚̏«—ˆ“W–]‚ƍ‚•ªŽqÞ—¿‚Ö‚ÌŠú‘ҁv, pp. 3-36, @iŽÐjƒGƒkEƒeƒB[EƒGƒX, 2004”N7ŒŽ2“úB

"Polymers in Micro Electronics," SPSJ (Ed.), H. Sunami(coauthor), "1. Scope of ULSI and expectatons to polymers," pp. 3-36 N. T. S., July 2, 2004.
13. uVLSIHŠw-»‘¢ƒvƒƒZƒX•Ò-v, “dŽqî•ñ’ʐMŠw‰ï•Ò, Šp“ì‰p•v’˜, 204•Å, iŠ”jƒRƒƒiŽÐ, 2006”N8ŒŽB
š –ÚŽŸ
"VLSI-Fabrication Process," IEICE, H. Sunami, 204 pagers, Corona Pub. Co., Aug. 2006.š contents .
14. u2007”Œ“±‘̃eƒNƒmƒƒW[‘å‘Sv, Electronic Journal•Êû, Šp“ì‰p•v‹€’˜, uƒLƒƒƒpƒVƒ^Œ`¬‹Zp‘˜_AƒXƒ^ƒbƒNƒgƒLƒƒƒpƒVƒ^Œ`¬‹Zpv, pp. 369-375, “dŽqƒWƒƒ[ƒiƒ‹ŽÐ, 2007”NB
"2007Semiconductor Technology Outlook," Electronic Journal Supplement, H. Sunami (coauthor), "Capacitor technology," pp. 369-375, Electronic Journal Pub. Co., 2007.
15. u’Ž‘å‹K–͏W¬“d˜H[Šî‘bEÝŒvE»‘¢H’öv, “dŽqî•ñ’ʐMŠw‰ï•Ò, Šâ“c–sAŠp“ì‰p•v‹€’˜, 309•Å, iŠ”j‰ÈŠwo”ŎЁA2008”N1ŒŽB
"VLSI-design & process," (Ed. : IEICE), A. Iwata & H. Sunami, 309 pages, Science Pub.(china), Jan. 2008.
16. u‹ZpŽÒ‚Ì‚œ‚ß‚Ì“Á‹–Ž–Žn[”Œ“±‘Ì‹Zp‚𒆐S‚Æ‚µ‚ā[v, Šp“ì‰p•v’˜, 149•Å,ƒRƒƒiŽÐ, 2008”N‚PŒŽB
š –ÚŽŸ
"Patent Application Guide for Engineers," H. Sunami, 149 pages, Corona Pub. Co., Jan 2008.
17. u”Œ“±‘̃ƒ‚ƒŠv, Šp“ì‰p•v’˜, 196•Å, ƒRƒƒiŽÐ, 2008”N8ŒŽBš –ÚŽŸ
"Semiconductor Memory," H. Sunami, 196 pages, Corona Pub. Co., Aug. 2008.
š contents
18. uƒƒ‚ƒŠƒfƒoƒCƒXE ƒCƒ[ƒWƒZƒ“ƒTv, Šp“ì‰p•vEìlË“ñ•Ò’˜, 292•Å, ŠÛ‘P, 2009”N12ŒŽB š –ÚŽŸ
"Memory Device and Image Sensor," H. Sunami (co-author) and S. kawahito, 292 pages, Maruzen, December 2009.
19. uSolid State Circuits Technologiesv, Šp“ì‰p•v’˜, "Dimension Increase in Metal-Oxide-Semiconductor Memories and Transistors," 1-26•Å, In-Tech, 2009”N12ŒŽB
"Solid State Circuits Technologies," H. Sunami (co-author), " Dimension Increase in Metal-Oxide-Semiconductor Memories and Transistors," 1-26 pages, In-Tech, Dec. 2009. @


Šwp˜_•¶ / Technical Journals
  1. M. Kumagawa, H. Sunami, T. Terasaki, and J. Nishizawa, gEpitaxial Growth with Light Irradiation,h Japan. J. Appl. Phys., Vol. 7, No. 11, pp. 1331-1341, 1968.
  2. H. Sunami, T. Terasaki, N. Miyamoto, and J. Nishizawa, gSurface Orientation Effect of the Shadow of the Stacking Fault, h J. Appl. Phys., Vol. 40, No. 11, pp. 4671-4673, 1969.
  3. H. Sunami, Y. Itoh, and K. Satoh, gStress and Thermal Expansion Coefficient of Chemica1-Vapor-Deposited Glass Films,h J. Appl. Phys. Vol. 41, No. 13, pp. 5115-5117, 1970.
  4. M. Tamura and H. Sunami, gGeneration of Dislocations Induced by Chemical Vapor Deposited Si3N4 Films on Silicon, h Japan. J. Appl. Phys. Vol. 11, No. 8, pp. 1097-1105, 1972.
  5. H. Sunami, Y. Kamigaki, and Y. Itoh, gA Charge Transfer Model in CCD and the Experimental Verification,h Trans. Inst. Electronics Comm. Engrs, Japan, Vol. 55, No. 11, pp. 26-27, 1972.
  6. Hideo Sunami, Yoshiaki Kamigaki, and Yokichi Itoh, "Charge Transfer Model of CCD and Its Experimental Verification, " (in Japanese) IEICE(C), Vol. 55-C, No. 11, pp. 586-593, 1972 (Šp“ì‰p•v, _Š_—Ǐº, ˆÉ“¡—e‹g, gCCD‚Ì“d‰×ˆÚ‘—ƒ‚ƒfƒ‹‚Æ‚»‚ÌŽÀŒ±“IŠmØ,h MŠw˜_(C), ‘æ55-CŠª, ‘æ11†, 586-593•Å, 1972).
  7. Y. Kamigaki, H. Sunami, and Y. Itoh, gBias Charge Optimization of High Speed CCD Operation,h Supplement to J. Japan Soc. Appl. Phys., Vol. 42, pp. 201-209, 1973.
  8. I. Takemoto, H. Sunami, S. Ohba, M. Aoki, and M. Kubo, gBulk Charge-Transfer Device,h Supplement to J. Japan Soc. App. Phys., Vol. 43, No. 8, pp. 264-268, 1974.
  9. P. E. Gregory, P. W. Chye, H. Sunami, and W. E. Spicer, gThe oxidation of Cs-uv photoemission studies, h J. Appl. Phys., Vol. 46, No. 8, pp. 3525-3529, 1975.
  10. P. W. Chye, T. Sukegawa, I. A. Babalola, H. Sunami, P. Gregory, and W. E. Spicer, gSurface and interface states of GaSb:A photoemission study, h Phys. Rev. B, Vol. 15, No. 4, pp. 2118-2126, 1977.
  11. T. Matsuzawa, H. Sunami, and N. Hashimoto, gAnalysis of Superposition Errors in Wafer Fabrication,h Microelectron. Reliab., Vol. 16, pp. 173-176, 1977.
  12. H. Sunami, gThermal Oxidation of Phosphorus Doped Polycrystalline Silicon in Wet Oxygen,h J. Electrochem. Soc., Vol. 125, No. 6, pp. 892-897, 1978.
  13. H. Sunami and M. Koyanagi, gSelective Oxide Coating of Silicon Gate (SELOCS),h Supplement to Japan. J. Appl. Phys., Vol. 18-1, pp. 255-260, 1979.
  14. M. Koyanagi, H. Sunami, and N. Hashimoto, gNovel High Density, Stacked Capacitor MOS RAM,h Supplement to Japan. J. Appl. Phys., Vol. 18-1, pp. 35-42, 1979.
  15. H. Sunami, M. Koyanagi, and T. Hashimoto, gIntermediate Oxide Formation in Double Polysilicon Gate MOS Structure,h J. Electrochem. Soc., Vol. 127, No. 11, pp. 2499-2506, 1980.
  16. H. Sunami, Y. Wada, and N. Hashimoto, gExperimental Characterization of MOSTes Scaled Down to the 1?m Level,h Microelectron. Reliab., Vol. 20, No. 6, pp. 803-822, 1980.
  17. Y. Wada, H. Sunami, and N. Hashimoto, gElectrical Testing for Process Evaluations,h Microelectron. Reliab., Vol. 21, No. 2, pp. 159-163, 1981.
  18. H. Sunami, K. Shimohigashi, and N. Hashimoto, gCharacterization of A Buried Channel Graded-Drain with Punchthrough Stopper (BGP) NMOS Device,h IEEE Trans. Electron Devices, Vol. ED-29, No. 4 , pp. 607-610, 1982.
  19. K. Itoh and H. Sunami, gHigh Density One-Device Dynamic MOS Memory Cells,h IEE Proc. 130, Pt. I, No. 3, pp. 127-135, 1983.
  20. H. Sunami, T. Kure, N. Hashimoto, T. Toyabe, and S. Asai, gA Corrugated Capacitor Cell (CCC) for Megabit Dynamic MOS Memories,h IEEE Electron Device Lett., Vol. EDL-4, No. 4, pp. 90-91, 1983.
  21. H. Sunami, K. Shimohigashi, and N. Hashimoto, gAn Optically Defined 1.3?m NMOS Ring Oscillator,h IEEE Electron Device Lett., Vol. EDL-4, No. 9, pp. 311-313, 1983.
  22. H. Sunami, T. Kure, N. Hashimoto, T. Toyabe, and S. Asai, gA Corrugated Capacitor Cell (CCC),h IEEE Trans. Electron Devices, Vol. ED-31, No. 6, pp. 746-753, 1984 (recipient of 1984 IEEE Paul Rppaport Award).
  23. H. Sunami, Y. Kawamoto, K. Shimohigashi, and N. Hashimoto, gAn Improved Planar Isolation with Buried-Channel MOSFETfs,h Microelectron. Reliab., Vol. 24, No. 3, pp. 555-577, 1984.
  24. K. Miyake, S. Kimura, T. Warabisako, H. Sunami, and T. Tokuyama, gMicrowave plasma stream transport system for low temperature plasma oxidation,h J. Vac. Sci. Tech. A, Vol. 2, No. 2, Part 1, pp. 496-499, 1984.
  25. R. Hori, K. Itoh, J. Etoh, S. Asai, N. Hashimoto, K. Yagi, and H. Sunami, gAn experimental 1Mbit DRAM based on high S/N design,h IEEE J. Solid State Circuits, Vol. SC-19, No. 5, pp. 634-640, 1984.
  26. K. Yamaguchi, R. Nishimura, T. Hagiwara, and H. Sunami, gTwo-Dimensional Numerical Model of Memory Devices with a Corrugated Capacitor Cell (CCC) Structure,h IEEE Trans. Electron Devices, Vol. ED-32, No. 2, pp. 282-289, 1985.
  27. S. Kimura, E. Murakami, K. Miyake, T. Warabisako, H. Sunami, and T. Tokuyama, gLow Temperature Oxidation of Silicon in a Microwave-Discharged Oxygen Plasma,h J. Electrochem. Soc., Vol. 132, No. 6, pp. 1460-1466, 1985.
  28. H. Sunami, T. Kure, K. Yagi, K. Yamaguchi, and S. Shimizu, gScaling Consideration and Dielectric Breakdown Improvement of Corrugated Capacitor Cell (CCC) for Future dRAM,h IEEE Trans. Electron Devices, Vol. ED-32, No. 2, pp. 296-303, 1985.
  29. M. Moniwa, M. Miyao, R. Tsuchiyama, A. Ishizaka, M. Ichikawa, H. Sunami, and T. Tokuyama, gPreferential nucleation along SiO2 steps in amorphous Si,h Appl. Phys. Lett., Vol. 47, No. 2, pp. 113-115, 1985.
  30. M. Ohkura, M. Ichikawa, M. Miyao, H. Sunami, and T. Tokuyama, gTwo-Dimensional Dynamic Numerical Simulation of an SOI Formation Process in Laser-Induced Seeded Lateral Growth,h IEEE Trans. Electron Devices, Vol. ED-32, No. 7, pp. 1347-1352, 1985.
  31. T. Matsuzawa, T. Ito, M. Tanuma, N. Hasegawa, and H. Sunami, gA Three Dimensional Photoresist Image Simulator : TRIPS-I,h IEEE Electron Device Lett., Vol. EDL-6, No. 8, pp. 416-418, 1985.
  32. S.-I. Kimura, E. Murakami, T. Warabisako, H. Sunami, anfd T. Tokuyama, gLow-Teperature Fabrication of MOSFETfs Utilizing a Microwave-Exicited Plasma Oxidation Technique,h IEEE Electron Device Lett., Vol. EDL-7, No. 1, pp. 38-40, 1986.
  33. T. Kure, T. Komoda, H. Sunami, S. Okazaki, and T. Hayashida, gEXAD: A Novel Electron-Beam X-ray Absorption Method of Nondestructive Depth Measurement for Silicon Trenches,h IEEE Electron Device Lett., Vol. EDL-7, No. 12, pp. 703-704, 1986.
  34. S. Yamamoto, T. Kure, H. Ohgo, T. Matsuzawa, S. Tachi, and H. Sunami, gA Two-Dimensional Etching Profile Simulator : ESPRIT,h IEEE Trans. Computer-Aided Design, Vol. CAD-6, No. 3, pp. 417-422, 1987.
  35. A. Moniwa, T. Matsuzawa, T. Ito, and H. Sunami, gA Three-Dimensional Photoresist Imaging Process Simulator for Strong Standing-Wave Effect Environment,h IEEE Trans. Compute-Aided Design, Vol. CAD-6, No. 3, pp. 431-438, 1987.
  36. H. Ohgo, Y. Takano, A. Moniwa, S. Yamamoto, Y. Sakai, H. Masuda, and H. Sunami, gA Two-Dimensional Integrated Process Simulator:SPIRIT-I,h IEEE Trans. Computer-Aided Design, Vol. CAD-6, No. 3, pp. 439-445, 1987.
  37. T. Matsuzawa, A. Moniwa, N. Hasegawa and H. Sunami, gTwo Dimensional Simulation of Photolithography on Reflective Stepped Surface,h IEEE Trans. Computer-Aided Design, Vol. CAD-6, No.3, pp.446-451, 1987.
  38. S. Kimura, E. Murakami, T. Warabisako, E. Mitani, and H. Sunami, gAn 18O study of oxygen exchange phenomena during microwave-discharge plasma oxidation of silicon,h J. Appl. Phys., Vol. 63, No. 9, pp.4655-4660, 1988.
  39. T. Kaga, Y. Kawamoto, T. Kure, Y. Nakagome, H. Aoki, H. Sunami, T. Makino, N. Ohki, and K. Itoh, gHalf-Vcc Sheath-Plate Capacitor DRAM Cell with Self-Aligned Buried Plate Wiring,h IEEE Trans. Electron Devices, Vol. 35, No. 8, pp. 1257-1263, 1988.
  40. M. Aoki, Y. Nakagome, M. Horiguchi, H. Tanaka, S. Ikenaga, J. Etoh, Y. Kawamoto, S. Kimura, E. Takeda, H. Sunami, and K. Itoh, gA 60-ns l6-Mbit CMOS DRAM with a Transposed Data-Line Structure,h IEEE J. Solid State Circuits, Vol. 23, No. 5, pp. 1113-1119, 1988.
  41. M. Ohkura, K. Kusukawa, and H. Sunami, gBeam Induced Seeded Lateral Epitaxy with Suppressed Impurity Diffusion for a Three-Dimensional DRAM Cell Fabrication,h IEEE Trans. Electron Devices, Vol. 36, No. 2, pp. 333-339, 1989.
  42. S. Kimura, Y. Kawamoto, T. Kure, N. Hasegawa, T. Kisu, J. Etoh, H. Aoki, E. Takeda, H. Sunami, and K. Itoh, gA Diagonal Active-Area Stacked Capacitor DRAM Cell with Storage Capacitor on Bit Line,h IEEE Trans. Electron Devices, Vol. 37, No. 3, pp. 737-743, 1990.
  43. Y. Takano, M. Ohgo, S. Yamamoto, and H. Sunami, gA versatile two-dimensional ion implantation simulator incorporated in an integrated process simulation system,h Microelectronic Engineering, Vol. 14, pp. 13-22, 1991.
  44. K. Itoh, H. Sunami, K. Nakazato, and M. Horiguchi, gPathways to DRAM Design and Technology for the 21st Century,h the 193rd Electrochemical Society Spring Meeting, Abs. No. 303, San Diego, California, May 3-8, 1998; Proceedings of the 8th Internat. Symp. Silicon Materials Science and Technology, Volume 98-1, pp. 350-369, 1998.
  45. (Hideo Sunami and Michio Suzuki, "Next generation integrated circuits fabrication line - future perspective of devicesand 300-mm in diameter fabrication line," (in Japanese), Aerosol Research, Vol. 14, No. 1, pp. 11-18, 1999 (Šp“ì‰p•v, —é–Ø“¹•v, uŽŸ¢‘ãWÏ‰ñ˜H‚Ɛ»‘¢ƒ‰ƒCƒ“ - ¡Œã‚̃fƒoƒCƒX“W–]‚Æ300mmƒEƒFƒn»‘¢ƒ‰ƒCƒ“‚Ì“®Œü - v,ƒGƒAƒƒ]ƒ‹Œ€‹†, ‘æ14Šª, ‘æ1†, pp. 11-18, 1999).
  46. A. Nakajima, T. Yoshimoto, T. Kidera, K. Obata, S. Yokoyama, H. Sunami, and M. Hirose, gAtomic-layer-deposited silicon-nitride/SiO2 stacked gate dielectriocs for highly reliable p-metal-oxide-semiconductor field-effect transistors,h Appl. Phys. Lett., Vol. 77, No. 18, pp. 2855-2857, 30 October 2000.
  47. A. Nakajima, T. Yoshimoto, T. Kidera, K. Obata, S. Yokoyama, H. Sunami, and M. Hirose, gCharacterization of atomic-layer-deposited silicon nitride/SiO2 stacked gate dielectrics for highly reliable p-metal-oxide-semiconductor field-effect transistors,h J. Vac. Sci. Tech. B, Vol. 19, pp. 1138-1143, 2001.
  48. Shin Yokoyama, Takenobu Yoshino, Kentaro Shibahara, Anri Nakajima, Takamaro Kikkawa, Hideo Sunami, and Quiz D. M. Khosru, "Influence of preservation ambient to MOS device characteristics," (in Japanese), Aerosol Research, Vol. 17, No. 2, , pp. 96-104, 2002 (‰¡ŽRV, ‹g–ì—YM,ŽÅŒŽŒ’‘Ÿ˜Y,’†“‡ˆÀ—,‹gìŒö–›,Šp“ì‰p•v, Quiz D. M. Khosru, “ƒEƒFƒn•ÛŠÇŠÂ‹«‚ÌMOSƒfƒoƒCƒX“Á«‚ւ̉e‹¿,” ƒGƒAƒƒ]ƒ‹Œ€‹†, ‘æ17Šª, ‘æ2†, pp. 96-104, 2002) .
  49. T. Furukawa, H. Yamashita, and H. Sunami, gA Proposal of Corrugated-Channel Transistor (CCT) with Vertically-Formed Channels for Area-Conscious Applications,h Jpn. J. Appl. Phys., Vol. 42, Part 1, No. 4B, pp. 2067-2072, April 2003.
  50. A. Takase, T. Kidera, and H. Sunami, gField-Shield Trench Isolation with Self-Aligned Field Oxide,h Jpn. J. Appl. Phys., Vol. 42, Part 1, No. 4B, pp. 2100-2105, April 2003.
  51. Hideo Sunami, "ULSI perspective and expectations to high polymer materials," (in Japanese), Vol. 52, No. 8, pp. 546-550A2003 (Šp“ì‰p•v,uULSI‚̏«—ˆ“W–]‚ƍ‚•ªŽqÞ—¿‚Ö‚ÌŠú‘Ò v, ‚•ªŽq, ‘æ52Šª, 8ŒŽ†, pp. 546-550A2003).
  52. Q. D. M. Khosru, S. Yokoyama, A. Nakajima, K. Shibahara, T. Kikkawa, H. Sunami, and T. Yoshino, gOrganic Contamination Dependence of Process-Induced Interface Trap Generation in Ultrathin Oxide Metal Oxide Semiconductor Transistors,h Jpn. J. Appl. Phys., Vol 42, Part 2, No. 12A, pp. L1429-L1432, 1 December 2003.
  53. H. Sunami, T. Furukawa, and T. Masuda, gA Three-Dimensional MOS Transistor Formation Technique with Crystallographic Orientation-Dependent TMAH Etchant,h SENSORS and ACTUATORS A: PHYSICAL, A111, pp. 310-316, 2004.
  54. A. Katakami, K. Kobayashi, and H. Sunami, gA High-Aspect Ratio Silicon Gate Formation Technique for Beam-Channel MOS Transistor with Impurity-Enhanced Oxidation,h Jpn. J. Appl. Phys., Vol. 43, No. 4B, pp. 2145-2150, April 2004.
  55. K. Kobayashi, T. Eto, K. Okuyama, K. Shibahara, and H. Sunami, "Application of Arsenic Plasma Doping in Three-Dimensional MOS Transistors and the Doping Profile Evaluation," Jpn. J. Appl. Phys., Vol. 44, No. 4B, pp. 2273-2278, April 2005.
  56. H. Sunami S. Matsumura, K. Yoshikawa, and K. Okuyama, "High-aspect-ratio structure formation techniques for three-dimensional metal-oxide-semiconductor transistors," Microelectronic Engineering, Vol. 83, pp. 1740-1744, 2006 .
  57. T. Tabei, K. Maeda, S. Yokoyama, and H. Sunami, "Fabrication of Spin-Coated Optical Waveguides for Optically Interconnected LSI and Influence of Fabrication Process on Underlying Metal-Oxide-Semiconductor Capacitors," Jpn. J. Appl. Phys., Vol. 45, No. 4B, pp. 3498-3503, 2006.
  58. Shunpei Matsumura, Atsushi Sugimura, Kiyoshi Okuyama, and Hideo Sunami, gAnomalous Whisker Generation in Ni-Silicided Source and Drain for Three-Dimensional Beam-Channel MOS Transistor on SOI Substrate,h Proc. of Advanced Metallization Conference 2006, pp. 631-635, ADMETA, 2007.
  59. Kei Kobayashi, Kiyoshi Okuyama, and Hideo Sunami, gPlasma doping induced damages associated with source/drain fomrmation in three-dimensional beam-channel MOS transistor,h Microelectronic Engineering, Vol. 84, pp. 1631-1634, 2007.@
  60. K. Okuyama, K. Yoshikawa, and H. Sunami, gControl of Subthreshold-Characteristics of Narrow- channel SOI nMOS Transistor Utilized Additional Side Gate Electrodes,h Jpn. J. Appl. Phys., Vol. 46, No. 4B, pp. 2050-2053, 2007.
  61. Hideo Sunami, gThe Role of the Trench Capacitor in DRAM Innovation,h IEEE SSCS News, Vol. 13, No.1, pp. 42-44, Winter 2008.
  62. Kiyoshi Okuyama, Atsushi Sugimura, and Hideo Sunami, gOptimized Silicidation Technique for Source and Drain of Fin-Type Field-Effect Transistor,h Jpn. J. Appl. Phys., Vol. 47, No. 4, pp. 2407-2409, 2008.
  63. Tomoki Hirata, Kenta Kajikawa, Tetsuo Tabei, and Hideo Sunami, gProposal of a Metal-Oxide- Semiconductor Silicon Optical Modulator Based on Inversion-Carrier Absorption,h Jpn. J. Appl. Phys., Vol. 47, No. 4, pp. 2906-2909, 2008.
  64. Kenta Kajikawa, Tetsuo Tabei, and Hideo Sunami, gAn infrared Silicon Optical Modulator of Metal-Oxide-Semiconductor Capacitor Based on Accumulation-Carrier Absorption,h Jpn. J. Appl. Phys., Vol. 48, No. 4, pp. 04C107-1-4, 2009.
  65. Atsushi Sugimura, Kiyoshi Okumura, Hideo Sunami, gProposal of a Vertical-Channel Metal Oxide Semiconductor Field-Effect Transistor with Entirely Oxidized Silicon Beam Isolation,h Jpn. J. Appl. Phys., Vol. 48, No. 4, pp. 04C049-1-4, 2009.
  66. Tetsuo Tabei, Tomoki Hirata, Kenta Kajikawa, and Hideo Sunami, gPotentiality of Metal-Oxide-Semiconductor Silicon Optical Modulator Based on Free Carrier Absorption,h Jpn. J. Appl. Phys., Vol. 48, No. 4, pp. 114501-1-7, 2009.
  67. T. Kudo, T. Kasama, S. Yokoyama, T. Kikkawa, H. Sunami, T. Ishikawa, T. Ikeda, Y. Hata, M. Suzuki, S. Tokonami, K. Okuyama, T. Tabei, K. Ohkura, Y. Kayaba, Y. Tanushi, Y. Amemiya, Y. Cho, T. Monzen, Y. Murakami, A. Kuroda, A. Nakajima, gFabrication of Si Nanowire FieldEffect Transistor for Highly Sensitive, LabelFree Biosensing,h Jpn. J. App. Phys. 48, No. 6, (2009) pp. 06FJ04-1-4.
  68. Yoichi Ashida, Kiyoshi Okuyama, and Hideo Sunami, "Preliminary characterization of a metal-gas-semiconductor field-effect transistor (MGSFET) proposed," Microelectronic Engineering, Vol. 88, pp. 213-217, 2011.


‘ÛŠw‰ï”­•\ / International Conference Presentation
  1. H. Sunami, Y. Itoh, and K. Sato, gStress and Thermal Expansion Coefficient of Chemical Vapor Deposited Glass Films,h Technical Digest of Symp. on Thermal Expansion of Solids, p. 45, Santa Fe, New Mexico, June 10-12, 1970.
  2. H. Sunami, Y. Itoh, and K. Sato, gLow Stress CVD Glass Films in Multi-Level Interconnection,h Proceedings of the 2nd Conference on Solid State Devices, Tokyo, Sept. 1970: Supplement to J. Japan Soc. Appl. Phys, Vol. 40, No. 8, pp. 67-70, 1971.
  3. Y. Kamigaki, H. Sunami, and Y. Itoh, gBias Charge Optimization of High Speed CCD Operation,h Proceedings of the 4th Conference on Solid State Devices, Abs. No. 6-4, Tokyo, Aug. 30-31, 1972.
  4. I. Takemoto, H. Sunami, S. Ohba, M. Aoki, and M. Kubo, gBulk Charge-Transfer Device,h Proceedings of the 5th Conference on Solid State Devices, Abs. No. 7-2, Tokyo, Aug 30-31, 1973.
  5. H. Sunami and M. Koyanagi, gSelective Oxide Coating of Silicon Gate (SELOCS) ,h? Proceedings of the 10th Conf. on Solid State Devices, pp. 67-68, Tokyo, Aug. 29-30, 1978.
  6. M. Koyanagi, H. Sunami, N. Hashimoto, and M. Ashikawa, gNovel High Density, Stacked Capacitor MOS RAM,h Technical Digest of IEEE Internat. Electron Devices Meeting, pp. 348-358, Washing-ton, D. C., Dec. 4-6, 1978.
  7. H. Sunami, K. Shimohigashi, and N. Hashimoto, gCharacterization of A Buried-Channel Graded-Drain with Punchthrough Stopper(BGP) MOS Device,h Technical Digest of Symp. on VLSI Technology, pp. 20-21, Hawaii, Sept. 1981.
  8. M. Koyanagi, T. Kamiyama, H. Sunami, and N. Hashimoto, gElectrical Properties of SiO2 Films in Double-Level Poly-Si Structures,h Extended Abstracts of the 155th Electrochemical Society Spring Meeting, Vol. 7-l, Abs. No. 87, pp. 225-227, May 6-11, 1979.
  9. K. Itoh and H. Sunami, gHigh Density Memory Cell Structure,h Technical Digest of Symp. on VLSI Technology, pp. 48-49, Hawaii, Sept. 1981.
  10. H. Sunami, T. Kure, N. Hashimoto, K. Itoh, T. Toyabe, and S. Asai, gA Corrugated Capacitor Cell (CCC) for Megabit Dynamic MOS Memories,h Technical Digest of IEEE Internat. Electron Devices Meeting, pp. 806-808, San Francisco, Dec. 13-15, 1982.
  11. K. Miyake, S. Kimura, T. Warabisako, H. Sunami, and T. Tokuyama, gMicrowave Plasma Stream Transport System for Photo Assisted Plasma Oxidation of Silicon Surfaces,h Proceedings of Internat. Ion Engineering Congress-ISIAT e83 and IPAT e83, pp. 915-920, Kyoto, 1983.
  12. Y. Wada, H. Sunami, N. Yamamoto, Y. Kawamoto, T. Mizutani, K. Yagi, Y. Homma, N. Hashimoto, and S. Asai, gA 1.3?m N-MOS VLSI Technology,h? Technical Digest of IEEE Internat. Electron Devices Meeting, pp. 323-325, Washington, Dec. 5-7, 1983.
  13. K. Yagi, H. Tamura, T. Kure, H. Sunami, N. Hashimoto, and S. Asai, gImprovement of Breakdown Characteristics of Storage Capacitor Insulating Materials,h Abstracts of Electronic Materials Conference, pp. 51-52, Vermont, 1983.
  14. H. Sunami, T. Kure, K. Yagi, K. Yamaguchi, and S. Shimizu, gScaling Consideration and Dielectric-Breakdown Improvement of Corrugated Capacitor Cell (CCC) for Future dRAMh Technical Digest of IEEE Internat. Electron Devices Meeting, pp. 232-235, San Francisco, Dec. 9-12, 1984.
  15. K. Itoh, R. Hori, J. Etoh, S. Asai, N. Hashimoto, K. Yagi, and H. Sunami, gAn Experimental 1Mbit DRAM with On-Chip Voltage Limiter,h Technical Digest of IEEE Internat. Solid-State Circuits Conf., pp. 282-283, San Francisco, Feb. 22-24, 1984.
  16. S. Kimura, E. Murakami, K. Miyake, T. Warabisako, and H. Sunami, gLow Temperature Oxidation of Silicon by Discharged Oxygen Plasma,h Proceedings of Internat. Conf. on Solid State Devices and Materials, Abs. No. A-11-3, pp. 467-470, Koube, Aug. 30-Sept. 1, 1984.
  17. H. Ohkura, H. Ichikawa, M. Miyao, H. Sunami, and T. Tokuyama, gDynamic Numerical Simulation of Melting and Resolidification Process in SOI Formation by Seeded Lateral Epitaxy.h Proceedings of Internat. Conf. on Solid State Devices and Materials, Abs. No. B-9-2, pp. 503-506, Koube, Aug. 30-Sept. 1, 1984.
  18. M. Miyao, M. Moniwa, M. Ichikawa, A. Ishizaka, T. Doi, H. Sunami, and T. Tokuyama, gNucleation Control and Epitaxial Alignment in Silicon On Insulator Structure during Solid Phase Growth,h Proceedings of Internat. Conf. on Solid State Devices and Materials, Abs. No. B-9-4, pp. 511-514, Koube, Aug. 30-Sept. 1, 1984.
  19. M. Miyao, M. Moniwa, T. Warabisako, H. Sunami, and T. Tokuyama, gFormation of Si-On-Insulator Structure under Solid Phase Growth,h Proceedings of Mat. Res. Soc. Symp., Vol. 35, pp. 705-709, Boston, Dec. 2-4, 1985.
  20. H. Sunami and S. Asai, gTrends in Megabit dRAMf s (Invited),h Technical Digest of the 2nd International Symp. on VLSI Technology, Systems and Applications, pp. 4-8, Taipei, May 8-10, 1985.
  21. H. Sunami, gCell Structures for Future dRAMes (Invited),h Technical Digest of IEEE Internat. Electron Devices Meeting, pp. 694-697, Washington, D. C., Dec. 1-4, 1985.
  22. K. Yamaguchi, R. Nishimura, T. Hagiwara, and H. Sunami, gTheoretical Characterization of Corrugated Capacitor Cell(CCC) Structure Devices by a Time-Dependent Numerical Analysis in Two Dimensions and Three-Dimensional DC Simulation,h Proceedings of 1985 Internat. Symposium on Circuits and Systems (ISCAS Ô85), Vol. 2 of 3, pp. 431-432, Kyoto, June 5-7, 1985.
  23. M. Ohkura, K. Kusukawa, H. Sunami, and T. Tokuyama, gOrientation Controlled SOI by Line Shaped Laser Beam Seeded Lateral Epitaxy for CMOS Stacking,h Extended Abstracts of the 17th Conf. on Solid State Devices and Materials , pp. 143-146, Tokyo, Aug. 25-27, 1985.
  24. E. Takeda, K. Takeuchi, A. Hiraiwa, T. Toyabe, H. Sunami, and K. Itoh, gThree Dimensional Leakage Current in Corrugated Capacitor Cells,h Extended Abstracts of the 17th Conf. on Solid State Devices and Materials, pp. 37-40, Tokyo, Aug. 25-27, 1985.
  25. M. Ohkura, K. Kusukawa, H. Sunami, T. Hayashida, and T. Tokuyama, gA Three-Dimensional DRAM Cell of Stacked Switching-Transistor in SOI(SSS),h Technical Digest of IEEE Internat. Electron Devices Meeting, pp. 718-721, San Francisco, Dec. 9-12, 1985.
  26. S. Kimura, E. Murakami, T. Warabisako, E. Mitani, and H. Sunami, gOxygen Exchange Phenomena in SiO2 During Microwave-Discharged Plasma Oxidation,h Abstracts of Fall Meeting of Materials Research Society Symposium, p. 112, Boston, Dec. 16, 1986.
  27. S. Kimura, Y. Kawamoto, N. Hasegawa, A. Hiraiwa, M. Horiguchi, H. Aoki, T. Kisu, and H. Sunami, gA 5.4 mm2 Stacked Capacitor DRAM Cell with 0.6mm Quadruple-Polysilicon Gate Technology,h Extended Abstracts of the 19th Conf. Solid-State Devices and Materials, pp. 19-22, Tokyo, Aug. 25-27, 1987.
  28. T. Kaga, Y. Kawamoto, T. Kure, Y. Nakagome, M. Aoki, T. Makino, and H. Sunami, gA 5.4 mm2 Sheath-Plate-Capacitor DRAM Cell with Self-Aligned Storage Node Insulation,h Extended Abstracts of the 19th Conf. Solid-State Devices and Materials, pp. 15-18, Tokyo, Aug. 25-27, 1987.
  29. T. Kure, T. Komoda, M. Noguchi, H. Sunami, and T. Hayashida, gDepth Measurement Techniques for Silicon Trenches,h Extended Abstracts of the 19th Conf. Solid-State Devices and Materials, pp. 307-310, Tokyo, Aug. 25-27, 1987.
  30. T. Kaga, Y. Kawamoto, T. Kure, Y. Nakagome, H. Aoki, H. Sunami, and K. Itoh, gA 4.2 mm2 Half-Vcc Sheath-Plate Capacitor DRAM Cell with Self-Aligned Buried Wiring,h Technical Digest of IEEE Internat. Electron Devices Meeting, pp. 332-335, Washington, D. C., Dec. 6-9, 1987.
  31. H. Sunami, T. Matsuzawa, M. Ohgo, and S. Yamamoto, gComputer-Aided Design of ULSI Processing Prior to Fabrication,h Extended Abstracts of the 171st Electrochem. Soc. Spring Meeting, Abs. No. 202, p. 291, Philadelphia, Pennsylvania, May 10-15, 1987 and Proceedings of the First International Symp. on Ultra Large Scale Integration Science and Technology, ULSI Science and Technology/1987, The Electrochemical Society, pp. 652-659.
  32. T. Kisu, S. Kimura, T. Kure, J. Yugami, A. Hiraiwa, Y. Kawamoto, M. Aoki, and H. Sunami, gA Novel Capacitance Enlargement Structure Using a Double-Stacked Storage Node in STC DRAM Cell,h Extended Abstracts of the 20th Conf. Solid State Devices and Materials, pp. 581-584, Tokyo, Aug. 24-26, 1988.
  33. H. Sunami, gMetrology for Trench Control,h 1988 Symposium on VLSI Technology, Special Workshop, San Diego, May 10, 1988.
  34. Y. Kawamoto, S. Kimura, N. Hasegawa, A. Hiraiwa, T. Kure, T. Nishida, M. Aoki, H. Sunami, and K. Itoh, gA Half Micron Technology for An Experimental 16 bit DRAM Using i-Line Stepper,h Symp. VLSI Technology Tech. Dig., pp. 17-18, May 10-13, San Diego, 1988.
  35. H. Sunami, gTechnology Trends in Dynamic RAMes:64Mb and Beyond (Invited),h the 21st Semiconductor Interface Specialists Conference, Abs. No. I-1, San Diego, Dec. 6-8, 1990.
  36. K. Itoh, H. Sunami, K. Nakazato, and M. Horiguchi, gPathways to DRAM Design and Technology for????? the 21st Century,h the 193rd Electrochemical Society Spring Meeting, Abs. No. 303, San Diego, California, May 3-8, 1998.
  37. H. Sunami, gPathways to Giga-scale Electronics for the 21st Century,h Seventh Hitachi Cambridge Seminar, Cambridge, July 6, 1998.
  38. T. Yoshino, S. Yokoyama, T. Suzuki, T. Fujii, K. Shibahara, A. Nakajima, T. Kikkawa, H. Sunami, and Q.D.M. Khosru, gInfluence of Organic Contamination on Reliability and Trap Generation in MOS,h Extend. Abst. of the Int. Conf. on Solid State Devices and Materials (Tokyo, 2001), pp. 176-177, 2001.
  39. H. Sunami, T. Furukawa, and T. Masuda, gOrientation-Dependent Anisotropic TMAH Etchant Applied to 3-D Silicon Nanostructure Formation,h Proc. Pacific Rim Workshop on Transducers and Micro/nano Technologies, pp. 367-372, Xiamen, July 22-24, 2002.
  40. T. Furukawa, H. Yamashita, and H. Sunami, gCorrugated-Channel Transistor (CCT) for Area-Conscious Applications,h Extended Abstracts of International Symp. on Solid State Devices and Materials, Abs. No. A-3-2, pp. 139-140, Nagoya, Sept. 17-19, 2002.
  41. A. Takase, T. Kidera, and H. Sunami, gField-Shield Trench Isolation with Self-Aligned Field Oxide,h Extended Abstracts of International Symp. on Solid State Devices and Materials, Abs. No. A-7-4, pp. 694-695, Nagoya, Sept. 17-19, 2002.
  42. A. Katakami, K. Kobayashi, and H. Sunami, gHigh-Aspect Ratio gate Formation of Beam-Channel MOS Transistor with Impurity-Enhanced oxidation of Silicon Gate,h Extended Abstracts of International Symp. on Solid State Devices and Materials, Abs. No. D-5-2, pp. 282-283, Tokyo, Sept. 16-18, 2003.
  43. K. Kobayashi, T. Eto, K. Okuyama, K. Shibahara, and H. Sunami, gAn Impurity-Enhanced Oxidation Assisted Doping Profile Evaluation for Three-Dimensional and Vertical-Channel Transistors,h Extended Abstracts of International Symp. on Solid State Devices and Materials, Abs. No. B-6-3, pp. 208-209, Tokyo, Sept. 15-17, 2004.
  44. M. Kawai, K. Endo, T. Tabei, and H. Sunami, gAn Experimental Analysis of 1.55-mm Infrared Light Propagation in Integrated SOI Structure,h Extended Abstracts of International Symp. on Solid State Devices and Materials, Abs. No. P7-1, pp. 556-557, Tokyo, Sept. 15-17, 2004.
  45. H. Sunami, K. Kobayashi, and S. Matsumura, gIntegrated Power Transistor Application of Three- Dimensional Sidewall-Channel MOS Transistor (invited),h Proc. the 7th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT 2004), Abs. No. A7.3, pp. 336-339, Beijin, China, Oct. 18-21, 2004.
  46. H. Sunami, gRecent Activities for Nano-device and Process Technology Development in the 21st COE: Nanoelectronics for Terabit Information Processing,h Tech. Dig. 2004 International Symposium on Nano Science and Technology, pp. 3-8, Tainan, Taiwan, Nov. 20-21, 2004.
  47. A. Iwata, M. Sasaki, T. Kikkawa, S. Kameda, H. Ando, K. Kimoto, D. Arizono, and H. Sunami, gA 3D Integration Scheme utilizing Wireless Interconnections for Implementing Hyper Brain,h ISSCC Tech. Dig., pp. 262-263, Feb. 2005.
  48. T. Tabei, K. Maeda, S. Yokoyama, and H. Sunami, gFabrication of spin-coat optical waveguides for optically interconnected LSI and influence of fabrication process on lower layer MOS capacitors,h Extended Abstracts of International Symp. on Solid State Devices and Materials, Abs. No. E-4-4, pp. 332-333, Tokyo, Sept. 13-15, 2005.
  49. H. Sunami and K. Okuyama, gHigh-Aspect-Ratio Structure Formation Techniques for Three- Dimensional Metal-Oxide-Semiconductor Transistors,h Abstract of 31st International Conference on Micro- and Nano-Engineering, No. 11B_03, Sept. 19-22, Vienna, Austria, 2005.
  50. K. Okuyama, K. Yoshikawa, and H. Sunami, gCharacterization of Subthreshold Behavior of Narrow-Channel SOI nMOSFET with Additional Side-Gate Electrodes,h Extended Abstracts of International Symp. on Solid State Devices and Materials, pp. 506-507, Tokyo, Sept. 13-15, 2006.
  51. Kei Kobayashi, Kiyoshi Okuyama, and Hideo Sunami, gPlasma-Doping Induced Damages Associated with Source/Drain Formation in Beam-Channel MOS Transistor on 1-mm Thick SOI Substrate,h Abstract of 32nd International Conference on Micro- and Nano-Engineering, pp. 493-494, Sept. 17-20, Barcelona, Spain, 2006.
  52. S. Matsumura, A. Sugimura, K. Okuyama, and H. Sunami, gAnomalous Whisker Generation in Ni-Silicided Source and Drain for Three-Dimensional Beam-Channel MOS Transistor on SOI Substrate,h Abstract of Advanced Metallization Conference, pp. 90-91, Sept. 25-27, Tokyo, 2006.
  53. K. Okuyama, K. Yoshikawa, and H. Sunami gProposal of 3-Dimensional Independent Triple-Gate MOS Transist with Dynamic Current Control,h 14th International Symposium on VLSI Technology, Systems, and Applications (2007 VLSI-TSA), Hsinchu, Taiwan, April 23-25, 2007.
  54. Kiyoshi. Okuyama, Atsushi. Sugimura, and Hideo Sunami, gAn Optimized Silicidation Technique for Source and Drain of FINFET,h Extended Abstracts of International Symp. on Solid State Devices and Materials, pp. 1044-1045, Tokyo, Sept. 19-21, 2007.
  55. Tomoki Hirata, Kenta Kajikawa, Tetsuo Tabei, and Hideo Sunami, gProposal of a Silicon Optical Modulator Based on Inversion-Carrier Absorption,h Extended Abstracts of International Symp. on Solid State Devices and Materials, pp. 280-281, Tokyo, Sept. 19-21, 2007.
  56. Tetsuo Tabei, Tomoki Hirata, Kenta Kajikawa, and Hideo Sunami, gPotentiality of Silicon Optical Modulator Based on Free-Carrier Absorption,h Technical Digest of IEEE Internat. Electron Devices Meeting, pp. 1023-1026, Washington, D. C., Dec. 10-12, 2007.
  57. Hideo Sunami, gThe invention and development of the first trench capacitor DRAM cell,h CMOS Emerging Technologies Workshop, Session 4, Vancouver, Canada, August 5-7, 2008.
  58. Youichi Ashida, Kiyoshi Okuyama, and Hideo Sunami, gProposal of a metal-gas-semiconductor field-effect transistor, MGSFET with potential catastrophic-breakdown hardness,h Abstract of 34th International Conference on Micro and Nano Engineering, Abs. No. NED-P16, Athens, Greece, Sept. 15-18, 2008.
  59. Atsushi Sugimura, Kiyoshi Okuyama, and Hideo Sunami, gA Vertical-Channel Metal-Oxide- Semiconductor Field-Effect Transistor with Fully-Oxidized Silicon Beam Isolation,h Extended Abstracts of International Symp. on Solid State Devices and Materials, P-3-8, Tokyo, Sept. 23-26, 2008.
  60. Kenta Kajikawa, Tetsuo Tabei, and Hideo Sunami, gSilicon Optical Modulator Based on Accumulation-Carrier Absorption of Metal-Oxide-Semiconductor Capacitor Waveguide,h Extended Abstracts of International Symp. on Solid State Devices and Materials, Abs. No. E-2-2, Tokyo, Sept. 23-26, 2008.
  61. Hideo Sunami, gDevelopment of three-dimensional MOS structures from trench-capacitor DRAM cell to pillar-type transistor,h Proc. the 9th International Conference on Solid-State and Integrated- Circuit Technology, pp. 853-856, Beijin, China, October 20-23, 2008.
  62. T. Tabei, K. Maeda, S. Yokoyama, and H. Sunami, gMonolithic Integaration of Si-Dot Light Emitting Diodes,h Extended Abstracts of International Symp. on Solid State Devices and Materials, Abs. No. I-2-d, Sendai, Oct. 7-9, 2009.


‘“àŠw‰ï”­•\ / Domestic Conference Presentation
  1. ŒFìªŽ¡A Šp“ì‰p•vAŒàVˆêAu‹C‘Š¬’·–@‚ɉ—‚¯‚éŒõÆŽË‚ÌŒø‰ ‚Ɛ¬’·‘w‚ÌŒ‹»«vAº˜a41”N“x“d‹C’ʐMŠw‰ï‘S‘‘å‰ïA—\eWNo. S86App. 155-156A1966”ND
  2. Šp“ì‰p•vAŒFìªŽ¡AŒàVˆêAuˆ ‘Š·Œ°”÷–@‹y‚Ñ‘œdŠ±Â–@‚ð—p‚¢‚œƒVƒŠƒRƒ“ƒGƒsƒ^ƒLƒVƒƒƒ‹¬’·•\– ‚ÌŠÏŽ@vA“dŽq’ʐMŠw‰ï‘n—§50Žü”N‹L”O‘S‘‘å‰ï(º˜a42”N“x) A—\eWNo. 777A1967”ND
  3. ŒFìªŽ¡AŠp“ì‰p•vAŽ›èŒ’AŒàVˆêAuƒVƒŠƒRƒ“‚Ì‹C‘Š¬’·‚É‚š‚¯‚éŒõÆŽË‚ÌŒø‰ ‚ÆŠiŽqŒ‡Š×v“dŽq’ʐMŠw‰ï”Œ“±‘́Eƒgƒ‰ƒ“ƒWƒXƒ^Œ€‹†‰ïAŽ‘—¿No. SSD67-11(1967-08) App. 1-15A1967”N8ŒŽ25“úD
  4. Šp“ì‰p•vAŽ›èŒ’AŒàVˆêAu‹C‘Š¬’·ƒVƒŠƒRƒ“Œ‹»’†‚̐ϑwŒ‡Š×vA“ú–{ŠwpU‹»‰ïA”––Œ‘æ131ˆÏŠL‰ïA‘æ38‰ñŒ€‹†‰ïŽ‘—¿No. 185App. 5-14A1968”N7ŒŽ20“úD
  5. ŒàVˆêAŒFìªŽ¡AŠp“ì‰p•vAuSi‹C‘ŠƒGƒsƒ^ƒLƒVƒ„ƒ‹¬’·‘w‚É‚š‚¯‚éŠiŽqŒ‡Š×vAº˜a43”N“d‹CŽlŠw‰ï˜A‡‘å‰ïA—\eWNo. S73App. 11-14A1968”ND
  6. Šp“ì‰p•vAŽ›èŒ’A‹{–{M—YAŒàVˆêAuƒVƒŠƒRƒ“‚Ì‹C‘Š¬’·‘w‚̍\‘¢Œ‡Š×vA“d‹CŠw‰ïAƒgƒ‰ƒ“ƒWƒXƒ^ê–åˆÏˆõ‰ïŽ‘—¿A1969”N1ŒŽ27“úD
  7. Šp“ì‰p•vAŽ›èŒ’A‹{–ؐM—YAŒàVˆêAuƒVƒŠƒRƒ“‚̃Gƒsƒ^ƒLƒVƒ„ƒ‹‘w‚̍\‘¢Œ‡Š×vA“dŽq’ʐMŠw‰ï”Œ“±‘́Eƒgƒ‰ƒ“ƒWƒXƒ^Œ€‹†‰ïAŽ‘—¿No. SSD69-10(1969-06)App. 1-15A1969”N6ŒŽ26“úD
  8. ˆÉ“¡—e‹gAŠp“ì‰p•vA_Š_—ǏºAuCharge Transfer Characteristics in CCDvA“ú–{ŠwpU‹»‰ïA”––Œ‘æ131ˆÏŠÑ‰ïA‘æ57‰ñŒ€‹†‰ïŽ‘—¿No. 307App. 1-3A1971”N12ŒŽ6“úD
  9. _Š_—ǏºAŠp“ì‰p•vAˆÉ“¡—e‹gAuCharge Transfer Model in CCD (1) TheoryvA1972”Nt‹G‘æ19‰ñ‰ž—p•š—Šw‰ïŠÖŒW˜A‡u‰‰‰ïA—\eWNo. 3a-C-3Ap. 365Aç—t‘åŠwA1972”N4ŒŽ3“úD
  10. ˆÉ“¡—e‹gAŠp“ì‰p•vA‚‰ªƒXƒ~ŽqA_Š_—ǏºAuCharge Transfer Model in CCD (1) Image @SimulationvA1972”Nt‹G‘æ19‰ñ‰ž—p•š—Šw‰ïŠÖŒW˜A‡u‰‰‰ïA—\eWNo. 3a-C-5Ap. 367Aç—t‘åŠwA1972”N4ŒŽ3“úD
  11. ˆÉ“¡—e‹gA_Š_—ǏºAŠp“ì‰p•vAuCCD‚̉摜ˆ—ƒVƒ~ƒ†ƒŒ[ƒVƒ‡ƒ“vAƒeƒŒƒrƒWƒ‡ƒ“Šw‰ïAƒeƒŒƒsƒWƒ‡ƒ““dŽq‘•’uŒ€‹†ˆÏˆõ‰ïŽ‘—¿App. 1-23A1973”N3ŒŽ7“úD
  12. _Š_—ǏºAŠp“ì‰p•vAˆÉ“¡—e‹gAuCCD‚É‚š‚¯‚éM†“d‰×‚̍жvA1973”Nt‹G‘æ20‰ñ‰ž—p•š—Šw‰ïŠÖŒW˜A‡u‰‰‰ïA—\eWNoD29a-P-3Ap. 237AŒc‰ž‘åŠwA“Œ‹žA1973”N3ŒŽ28-31“úD
  13. Šp“ì‰p•vAˆÉ“¡—e‹gA²“¡Šì‹vŽ¡Au‘œ‘w”züWÏ‰ñ˜H‚̒቞—̓Kƒ‰ƒXâ‰–Œvº˜a45”N“x“dŽq’ʐMŠw‰ï‘S‘‘å‰ïA—\eWNo. 708Ap. 767A1970”N8ŒŽD
  14. Šp“ì‰p•vAˆÉ“¡—e‹gAu”Œ“±‘Ì‘fŽq‚É—p‚¢‚ç‚ê‚é”––Œ‚̐^«‰ž—Í‚Æ”M–c’£ŒW”‚Ì‘ª’è–@vAº˜a46”N“d‹CŠw‰ï‘S‘‘å‰ïA—\eWNo. 1166Ap. 577A“¿“‡‘åŠwA1971”N3ŒŽD
  15. Šp“ì‰p•vA_Š_—ǏºAˆÉ“¡—e‹gAuCCD‚É‚æ‚é“d‰×ˆÚ‘—‚Ì“®ìŽÀŒ±vA1971”N(º˜a46”N) H‹G‘æ32‰ñ‰ž—p•š—Šw‰ïŠwpu‰‰‰ïA—\eWNo. 1a -H-5Ap. 158A‘åã‘åŠwA‘åãA1971”N11ŒŽ1“úD
  16. Šp“ì‰p•vA_Š_—ǏºAˆÉ“¡—e‹gAuCCD‚Ì“d‰×ˆÚ‘—‹@\vA“dŽq’ʐMŠw‰ï”Œ“±‘́Eƒgƒ‰ƒ“ƒWƒXƒ^Œ€‹†‰ïAŽ‘—¿No. SSD71-68(1972-02) App. 1-14A1972”N2ŒŽ24“úD
  17. Šp“ì‰p•vA_Š_—ǏºAˆÉ“¡—e‹gAuCCD‚É‚š‚¯‚é“d‰×ˆÚ‘—ƒ‚ƒfƒ‹vAº˜a47”N“dŽq’ʐMŠw‰ï‘S‘‘å‰ïA—\eWNo. 976Ap. 1048A“Œ‹žA1972”N3ŒŽD
  18. Šp“ì‰p•vA_Š_—ǏºAˆÉ“¡—e‹gAun-ƒ`ƒƒƒlƒ‹CCD‚ÌŠî‘bŽÀŒ±vA1973”Nt‹G‘æ20‰ñ‰ž—p•š—Šw‰ïŠÖŒW˜A‡u‰‰‰ïA—\eWNo. 29a-P-2Ap. 236AŒc‰ž‘åŠwA“Œ‹žA1973”N3ŒŽ28-31“úD
  19. Šp“ì‰p•vA_Š_—ǏºAˆÉ“¡—e‹gAuCCD“d‰×ˆÚ‘—‚̃oƒCƒAƒX“d‰×Œø‰ vA1975”Nt‹G‘æ22‰ñ‰ž—p•š—Šw‰ïŠÖŒW˜A‡u‰‰‰ïA—\eWNo. 2a-C-2Ap. 39Aç—tH‹Æ‘åŠwAç—tA1975”N4ŒŽ14“úD
  20. Šp“ì‰p•vA¬–öŒõ³AuƒVƒŠƒRƒ“ƒQ[ƒg‚Ì‘I‘ðŽ_‰»–Œ”í•¢‹Zp(SELOCS) vA“dŽq’ʐMŠw‰ï”Œ“±‘́Eƒgƒ‰ƒ“ƒWƒXƒ^Œ€‹†‰ïAŽ‘—¿No. SSD77-26App. 27-36A1977”N8ŒŽ24“úD
  21. Šp“ì‰p•vAuƒŠƒ““Y‰Á‘œŒ‹»ƒVƒŠƒRƒ“‚Ì”MŽ_‰»‹@\vA1978”NH‹G‘æ39‰ñ‰ž—p•š—Šw‰ïŠwpu‰‰‰ïA—\‹ŽWANo. 5a-X-6Ap. 433A‹ß‹E‘åŠwA‘åãA1978”N11ŒŽ3-5“úD
  22. Šp“ì‰p•vA˜a“c‹±—YA‹Ž–{“NˆêAu’Zƒ`ƒƒƒlƒ‹—̈æ‚É‚š‚¯‚éMOSƒgƒ‰ƒ“ƒWƒXƒ^‚ÌŽÀŒøˆÚ“®“xvA1979”NH‹G‘æ40‰ñ‰ž—p•š—Šw‰ïŠwpu‰‰‰ïA—\eWNo. 1a-L-10A–kŠC“¹‘åŠwA1979”N9ŒŽ30“ú-10ŒŽ2“úD
  23. Šp“ì‰p•vA‹vâX“Ÿ’jA‹Ž–{“NˆêAˆÉ“¡Ž’jAóˆä²“ñ˜YAuVƒ_ƒCƒiƒ~ƒbƒNƒƒ‚ƒŠƒZƒ‹FCCC (Corrugated Capacitor Cell) vA“d‹CŠw‰ï‘æ6‰ñ”Œ“±‘̃fƒoƒCƒX’²žê–åˆÏˆõ‰ïA“Œ‹ž‘åŠw¶ŽY‹ZpŒ€‹†ŠA1983”N2ŒŽl0“úD
  24. Šp“ì‰p•vA‹vâX“Ÿ’jA‹Ž–{“NˆêAˆÉ“¡Ž’jAóˆä²“ñ˜YAuVƒ_ƒCƒiƒ~ƒbƒNƒƒ‚ƒŠƒZƒ‹FCCCvAº˜a58”N“x“dŽq’ʐMŠw‰ï‘‡‘S‘‘å‰ïA—\eWNo. S2-6App. 413-414A1983”N4ŒŽ2-4“úD
  25. ‘å‘q—AŽsì”©˜aA‹{”ö³MAŠp“ì‰p•vAuƒŒ[ƒU[ÆŽËSOIŒ`¬‚ÌŒvŽZ‹@ƒVƒ~ƒ†ƒŒ[ƒVƒ‡ƒ“vA1984”Nt‹G‘æ31‰ñ‰ž—p•š—Šw‰ïŠÖŒW˜A‡u‰‰‰ïA—\eWNoD31a -U-2Ap. 443A–ŸŽ¡‘åŠwA“Œ‹žA1984”N3ŒŽ29“ú-4ŒŽ2“úD
  26. “íìŠì‹v—YA‘å‘q—A‹{”ö³MAŠp“ì‰p•vAuƒŒ[ƒU[ÆŽËSOIŒ`¬‚̉º‘w\‘¢‚ւ̉e‹¿vA1984”Nt‹G‘æ31‰ñ‰ž—p•š—Šw‰ï‰{ŒW˜A‡u‰‰‰ïA—\eWNo. 31p-U-10Ap. 449A–ŸŽ¡‘åŠwA“Œ‹žA1984”N3ŒŽ29“ú-4ŒŽ2“úD
  27. –Ø‘ºaˆê˜YA‘ºã‰pˆêA˜n”—Œõ‹IAŽO‘AŠp“ì‰p•vAu—LŽ¥êƒ}ƒCƒNƒ”gƒvƒ‰ƒYƒ}‚É‚æ‚éƒVƒŠƒRƒ“‚̒ቷŽ_‰»(I) vA1984”Nt‹G‘æ31‰ñ‰ž—p•š—Šw‰ïŠÖŒW˜A‡u‰‰‰ïA—\eWNo. 1p-U-1Ap. 45A–ŸŽ¡‘åŠwA“Œ‹žA1984”N3ŒŽ29“ú-4ŒŽ2“úD
  28. ‘ºã‰pˆêA––‘ºaˆê˜YAŽO‘A˜n”—Œõ‹IAŠp“ì‰p•vAu—LŽ¥êƒ}ƒCƒNƒ“nƒvƒ‰ƒYƒ}‚É‚æ‚éƒVƒŠƒRƒ“‚̒ቷŽ_‰»(II) vA1984”Nt‹G‘æ31‰ñ‰ž—p•š—Šw‰ïŠÖŒW˜A‡u‰‰‰ïA—\eWNo. 1p-U-2Ap. 455A–ŸŽ¡‘åŠwA“Œ‹žA1984”N3ŒŽ29“ú-4ŒŽ2“úD
  29. ŽRŒûŒ›AŒ‘º—æŽqA”‹ŒŽ—²ŠŽAŠp“ì‰p•vAuƒƒKƒrƒbƒg‹‰d RAM—paŒ^ƒLƒ„ƒpƒVƒ^‚Ì“ñŽŸŒ³‰ß“n‰ðÍvA1984”NH‹G‘æ45‰ñ‰ž—p•š—Šw‰ïŠwpu‰‰‰ïA—\eWNo. 14a-A-10Ap. 409A‰ªŽR‘åŠwA1984”N10ŒŽ12“ú-15“úD25) Šp“ì‰p•vAud RAM‚ÌŒÀŠEF‘Ÿ‹K–͉»‚ð–W‚°‚éˆöŽq‚ƃuƒŒ[ƒNƒXƒ‹[vA@“ú–{“dŽqH‹ÆU‹»‹Š‰ïA“dŽqƒfƒoƒCƒXu‰‰‰ïA‹@ŠBU‹»‰ïŠÙA“Œ‹žA1985”N7ŒŽ1“úD
  30. ŽRŒûŒ›AŒ‘º—æŽqA”‹ŒŽ—²ŠŽAŠp“ì‰p•vAuaŒ^ƒLƒƒƒpƒVƒ^ƒZƒ‹‚ÌŽOŽŸŒ³“®ì‰ðÍvA‘æ32‰ñt‹G‰ž—p•š—Šw‰ïŠÖŒW‰^‡u‰‰‰ïA—\eWNo. la-E-9Ap. 551AÂŽRŠw‰@‘åŠwA“Œ‹žA1985”N3ŒŽ29“ú-4ŒŽl“úD
  31. –Ø‘ºaˆê˜YA‘ºã‰pˆêA˜n’ÇŒõ‹IAŠp“ì‰p•vAuƒ}ƒCƒNƒ”gƒuƒ‰ƒYƒ}‚É‚æ‚éƒVƒŠƒRƒ“‚̒ቷŽ_‰»vA“d‹CŠw‰ïAƒvƒ‰ƒYƒ}Œ€‹†‰ïŽ‘—¿No. EP-85-3App. 17-24A1985”N6ŒŽ18“úD
  32. ’|“àŠ²A•“c‰pŽŸA•œŠâ“āA’¹’J•”’BAŠp“ì‰p•vAˆÉ“¡Ž’jAuaŒ^ƒLƒƒƒpƒVƒ^‚É‚š‚¯‚éŽOŽŸŒ³ƒŠ[ƒN“d—¬vAº˜a60”NH‹G‘æ46‰ñ‰ž—p•š—Šw‰ïŠwpu‰‰‰ïA—\eWNo. 4a-V-6Ap. 422A‹ž“s‘åŠwA‹ž“sA1985”N10ŒŽl“ú-4“úD
  33. Šp“ì‰p•vAu0.5mmŽž‘ã‚̃vƒƒZƒXEƒfƒoƒCƒXvAº˜a63”N“x“dŽqî•ñ’ʐMŠw‰ït‹G‘S‘‘å‰ï“Á• Šé‰æAƒGƒŒƒNƒgƒƒjƒNƒXƒOƒ‹[ƒuuK‰ïu0.5mm ULSIƒeƒNƒmƒƒW[v—\eWApp. 25-34A‘ˆî“c‘åŠwA“Œ‹žA1988”N3ŒŽ29“úD
  34. ‰Á‰ê“OAì–{‰ÀŽjA’†ž‹V‰„AÂ–ؐ³˜aAŠp“ì‰p•vA–q–ì“¡”ªA‘å–Ø’·“lŽiAˆÉ“¡Ž’jAuƒn[ƒtVccâƒvƒŒ[ƒg—e— Œ^DRAMƒZƒ‹vAº˜a63”N“x“dŽq’ʐMŠw‰ït‹G‘S‘‘å‰ï—\eWAp. 2-181A‘ˆî“c‘åŠwA“Œ‹žA1988”N3ŒŽ28“ú-31“úD@
  35. Šp“ì‰p•vAuƒVƒŠƒRƒ“ƒfƒoƒCƒX‚̏«—ˆ‚ÆŠÖ˜AŠî‘bŒ€‹†‚Ì‚ ‚é‚ׂ«Žp‚ɂ‚¢‚āvA(à) V‹@”\‘fŽqŒ€‹†ŠJ”­‹Š‰ïA‘æ1‰ñ’Ž‚WÏ‘fŽqŒ€‹†ˆÏ–á‰ïu‰‰‰ïA“Œ‹žA1989”N4ŒŽ17“úD
  36. Šp“ì‰p•vAuƒVƒŠƒRƒ“ULSI‚ÌŒ»ó‚Ə«—ˆvA“dŽqî•ñ’ʐMŠw‰ïu‰‰‰ïA•xŽR‘åŠwA•xŽRA1989”N5ŒŽ19“úD
  37. Šp“ì‰p•vAuULSIŽž‘ã‚̃VƒŠƒRƒ“ƒeƒNƒmƒƒW[vA‰ž—p•š—Šw‰ïA‘æ17‰ñ”––ŒE•\– •š–„ƒZƒ~ƒi[—\eWAp. 112A‹@ŠBU‹»‰ïŠÙA“Œ‹žA1989”N7ŒŽ19“úD
  38. Šp“ì‰p•vAu21¢‹I‚ÌDRAMƒƒ‚ƒŠƒZƒ‹‹ZpvA•œ¬9”N“x“d‹CŠw‰ïA“dŽqEî•ñEƒVƒXƒeƒ€•”–å‘å‰ïA—\eWApp. 31-34A¬æü‘åŠwA“Œ‹žA1997”N8ŒŽ28“úD
  39. ‚£–Ÿ_AŠp“ì‰p•vAuLSI‘fŽq•ª—£‚É‚š‚¯‚éƒGƒbƒWŒø‰Ê‚̒ጞvA‘æ61‰ñ‰ž—p•š—Šw‰ïŠwpu‰‰‰ïA—\eWNo. 5p-ZE-5Ap. 782A–kŠC“¹H‹Æ‘åŠwAŽD–yA2000”N9ŒŽ3“ú-9ŒŽ7“úD
  40. ŒÃì’qNAŠp“ì‰p•vAuƒr[ƒ€ƒ`ƒƒƒlƒ‹MOSFET‚É‚æ‚éÔŠOŒõƒXƒCƒbƒ`‚Ì’ñˆÄvA‘æ61‰ñ‰ž—p•š—Šw‰ïŠwpu‰‰‰ïA—\eWNo. 6p-ZK-1Ap. 1227A–kŠC“¹H‹Æ‘åŠwAŽD–yA2000”N9ŒŽ3“ú-9ŒŽ7“úD
  41. •Ðã˜NA‚£–Ÿ_AŠp“ì‰p•vAuƒr[ƒ€ƒ`ƒƒƒlƒ‹MOSFET‚É‚š‚¯‚éƒQ[ƒgŒ`¬ƒvƒƒZƒXvA‘æ62‰ñ‰ž—p•š—Šw‰ïŠwpu‰‰‰ïA—\eWNo. 13a-P9-9Ap. 688Aˆ€’mH‹Æ‘åŠwA–ŒŒÃ‰®A2001”N9ŒŽ11“ú-9ŒŽ14“úD
  42. ŒÃì’qNAŠp“ì‰p•vAu‚‚¢“d—¬‹ì“®”\—Í‚ðŽÀŒ»‚·‚éBeam-Channel-MOSFET‚Ì“d‹C“Á«v‘æ49‰ñ‰ž—p•š—Šw‰ïŠÖŒW˜A‡u‰‰‰ïA—\eWNo. 30a-H-9Ap. 894A“ŒŠC‘åŠwA_“ސìA2002”N3ŒŽ27“ú-3ŒŽ30“úD


‰ðà‹LŽ– / Review Articles
  1. ˆÉ“¡—e‹g, Šp“ì‰p•v, _Š_—Ǐº, uCCD‚É‚š‚¯‚é“d‰×ˆÚ‘—Œø—Šv‰ž—p•š—, ‘æ41Šª, ‘æ294†, 192-194•Å, 1972”N
  2. Šp“ì‰p•vAuŠCŠO˜_•¶Ð‰îF“d‹ÉŠÔŠÔŒ„‰º‚É–„ž‚݃`ƒƒƒlƒ‹‚ð‚à‚ÂCCDvA“dŽq’ʐMŠw‰ïŽA‘æ56ŠªA10†App. 1414-1415A1973”N10ŒŽ.
  3. Šp“ì‰p•v;Au1981 Symposium on VLSI TechnologyvA“dŽq’ʐMŠw‰ïŽA‘æ64ŠªA12†Ap. 1289A1981”N12ŒŽ.
  4. Šp“ì‰p•vAu1983 IEEE International Solid-State Circuits Conference ('83 ISSCC)vA“dŽq’ʐMŠw‰ïŽA‘æ66ŠªA5†Ap. 459A1983”N5ŒŽ.
  5. ˆÉ“¡Ž’jAŠp“ì‰p•v;Au‚WÏƒ_ƒCƒiƒ~ƒbƒNRAMŽÀŒ»‚ÌŠî‘b‚ƂȂ郁ƒ‚ƒŠEƒZƒ‹‚̐݌vvA“úŒoƒGƒŒƒNƒgƒƒjƒNƒXApp. 169-193, 1983”N7ŒŽ3“ú†.
  6. Šp“ì‰p•v;AˆÉ“¡Ž’jAóˆä²“ñ˜YAu—§‘̃Zƒ‹\‘¢‚É‚æ‚éMƒsƒbƒg‹‰ƒ_ƒCƒiƒ~ƒbƒNRAM‹ZpvA“ú—§•]˜_A66ŠªA1984”N1ŒŽ†Ap. 4.
  7. Šp“ì‰p•vAuIEDM '84vAƒeƒŒƒrƒWƒ‡ƒ“Šw‰ïŽA‘æ39ŠªA‘æ3†App. 259-260A1985”N.
  8. ‹Ž–{“NˆêA‘ŒŽ—˜–ŸAŠp“ì‰p•vA”‹ŒŽ—²ŠŽA–x’r–õ_A‚{Vˆê˜YAuƒfƒoƒCƒX‚Í0.2mm‚Ü‚ÅŒ©’Ê‚¹‚邪AƒvƒƒZƒX‚ÍŒõ˜IŒõ‚̐悪Œ©‚Š‚È‚¢vA“úŒoƒ}ƒCƒNƒƒfƒoƒCƒXA1985”N7ŒŽ(‘nŠ§) †App. 131-155.
  9. Šp“ì‰p•vAu1985 IEDM‚É‚Ý‚éMbitƒƒ‚ƒŠ‘fŽqvAULSIApp. 33-36A1986”N3ŒŽ†.
  10. Šp“ì‰p•vAu‘æ18ŒÅŒÅ‘Ì‘fŽqEÞ—¿ƒRƒ“ƒtƒ@ƒŒƒ“ƒX•ñvASEMICON NEWSA1986.11†App. 82-87A1986”N.
  11. Šp“ì‰p•vAu‘å‹K–͉»‚·‚éDRAM‚𒆊j‚É“WŠJvA“ú–{‚̉Ȋw‚Æ‹Zpf86^ƒƒ‚ƒŠApp. 39-45A1986”N.
  12. Šp“ì‰p•v, ‰i“cõ,uƒfƒoƒCƒXWÏ‰»‚Ì‹ÉŒÀvA‰ž—p•š—A‘æ55ŠªA ‘æ4†A 349-353•ÅA 1986”N.
  13. H. Sunami, gThe State of the Art in Megabit Memory Technology : Critical Reviews of 4Mbit DRAM Technology, Cell Structures," JST Reports, Vol. 3, No. 1, pp. 21-26, Spring 1987.
  14. Šp“ì‰p•vAu4MA16MDRAM‚̍s•û-Ï‘w—e—ʂƍaŒ`—e—ʁvAŒŽŠ§Semiconductor WorldA1988”N2ŒŽ†App. 31-36.
  15. Šp“ì‰p•vAu16MƒrƒbƒgDRAMvAƒGƒŒƒNƒgƒƒjƒNƒXA1988”N1ŒŽ†App. 30-34.
  16. ì–{‰ÀŽj, ‹vâX“Ÿ’j, Œ“c‚, Šp“ì‰p•v, uƒgƒŒƒ“ƒ`‚É‚àƒXƒ^ƒbƒN‚É‚à‰ðA”zü‚̓VƒŠƒTƒCƒh{2‹ûAlv, “úŒoƒ}ƒCƒNƒƒfƒoƒCƒXA1988”N4ŒŽ†App. 46-51.
  17. Šp“ì‰p•v, _ŒËG, {²M•F, ÎŒŽG, u‘ÛŒÅ‘Ì‘fŽqEÞ—¿ƒRƒ“ƒtƒ@ƒŒƒ“ƒX•ñvA‰ž—p•š—A‘æ57ŠªA11†App. 1773-1775A1988”N.
  18. Šp“ì‰p•v, u1 Gbit’ŽXLSI‚̉”\«vA‹Zp—\‘ªƒVƒŠ[ƒYA‘æ3ŠªA“ú–{ƒrƒWƒlƒXƒŒƒ|[ƒg(Š”)App. 1-6A1989”N.
  19. Šp“ì‰p•v, uƒXƒ^ƒbƒNAƒgƒŒƒ“ƒ`—ŒŽÒ‚ɉðvA“úŒoƒ}ƒCƒNƒƒfƒoƒCƒXAp. 48A1989”N5ŒŽ†.
  20. Šp“ì‰p•v, u‘æ4.2ßFƒVƒŠƒRƒ“ƒfƒoƒCƒX‚Ì”÷×‰»vA21¢‹I’Ž‚WÏ‘fŽq‚ÉŠÖ‚·‚錀‹†•ñ‘(ƒiƒmƒ[ƒ^‹@”\‘fŽq‚ð‚ß‚®‚Á‚Ä)App.37-42A(à)V‹@”\‘fŽqŠJ”­Œ€‹†‹Š‰ïA1989”N6ŒŽ.
  21. Šp“ì‰p•v, u”zü‚ÍTiWATiN‚ÆAl-SiŒnAÏ‘wƒŠƒ\ƒOƒ‰ƒtƒB‚ÍFLEX–@‚ª—L–]vAŒŽŠ§Semiconductor WorldApp. 150-159A1989”N7ŒŽ†.
  22. Šp“ì‰p•vAu256M‚ŃZƒ‹‚ª•Ï‚í‚évA“úŒoƒ}ƒCƒNƒƒfƒoƒCƒXA1989”N8ŒŽ†App. 134-135.
  23. Šp“ì‰p•v, –ì“c‰x•v, ’ÃŽç–M•F, ’†’i˜aG, M‘ŸŽ‹K, ˆÉ“¡‰ë‰p, “c‘ã‰p•v, ‰Í“úmŽi, ‰Í’ÏŸ, ŒÃŽº”©“¿, ¯—zˆêv—é–ØŽÀ, ’†Œ”ª˜Y, •“cK—ß, ‹g–ì~“ñ, ‘Ÿ“cŒöœA, “ˆ“cŽõˆê, ’rè˜a’j, u‘æ37‰ñ‰ž—p•š–„ŠwŠÖŒW˜A‡u‰‰‰ï(1990”N)v, ‰ž—p•š—, ‘æ59Šª, ‘æ6†, pp. 768-783, 1990”N.
  24. Šp“ì‰p•v, Œã“¡r•v, ’†’i˜aG, t–Œ³Œõ, ˆÉ“¡ˆê—Ç, Î“c—SŽO, ‘å’ÃŒ³ˆê, ‘êìŒbG, ŽRè—z‘Ÿ˜Y, —é–ØŽÀ, ’†Œ”ª˜Y, Œ‰i€ˆê, ’†ìŠi, Žº’J—˜•v, –{ŠÔŠi, ‘å‘ò•q•F, š ’J•Û—Y, u‘æ51‰ñ‰ž—p•š—Šw‰ïŠwpu‰‰‰ï(1990”N)v, ‰ž—p•š—, ‘æ60Šª, ‘æ1†, pp. 70-81, 1991”N.
  25. Šp“ì‰p•vAu‘Ÿ—z“d’r‚̍\‘¢‚ªƒqƒ“ƒg‚ɁvA“úŒoƒ}ƒCƒNƒƒfƒoƒCƒXA1993”N12ŒŽ†App. 203-204.
  26. Šp“ì‰p•v, uƒMƒKEƒrƒbƒgDRAMŽž‘ã‚̐V‚µ‚¢ƒXƒP[ƒŠƒ“ƒO‘¥vA“úŒoƒ}ƒCƒNƒƒfƒoƒCƒXA1996”N12ŒŽ†App. 112-123..
  27. Šp“ì‰p•v, u‘•]F”Œ“±‘̂̉ȊwvA“úŒoƒ}ƒCƒNƒƒfƒoƒCƒXAp. 25A1997”N6ŒŽ†.
  28. Šp“ì‰p•vAu¢“ï‚É‚È‚éƒZƒ‹”÷×‰»‚ðVÞ—¿‚ŏæ‚èØ‚évA“úŒoƒ}ƒCƒNƒƒfƒoƒCƒXA1997”N12ŒŽ†App. 144-157.
  29. Šp“ì‰p•vA—é–Ø“¹•vAuŽŸ¢‘ãWÏ‰ñ˜H‚Ɛ»‘¢ƒ‰ƒCƒ“ - ¡Œã‚̃fƒoƒCƒX“W–]‚Æ30mmƒEƒFƒn»‘¢ƒ‰ƒCƒ“‚Ì“®Œü -vAƒGƒAƒƒ]ƒ‹Œ€‹†A‘æ14ŠªA‘æ1†App. 11-18A1999.
  30. Šp“ì‰p•vAuLSI‹Zp‚ðÞ—¿–Ê‚©‚ç‚Æ‚ç‚Š‚é:‘•]w”Œ“±‘̂̉»ŠwxvA“úŒoƒ}ƒCƒNƒƒfƒoƒCƒXA1997”N6ŒŽ†Ap. 25.
  31. ‰¡ŽRVAŽÅŒŽŒ’‘Ÿ˜YA’†“‡ˆÀ—A‹gìŒö–›AŠp“ì‰p•vAQuazi D. M. KhosruA‹g–ì—YMAuƒVƒŠƒRƒ“”MŽ_‰»–Œ‚̃zƒbƒgƒGƒŒƒNƒgƒƒ“‘ϐ«‚É‹y‚Ú‚·—L‹@ƒKƒX‰˜õ‚̉e‹¿vMŠw‹Z•ñSDM2001-47, pp. 19-24, 2001.
  32. Šp“ì‰p•vAuVÞ—¿EV\‘¢‚𓱓ü‚µ‚WÏ‰»‚Ì•Ç‚ð‘Å”jvA“úŒoƒ}ƒCƒNƒƒfƒoƒCƒXA2006”N3ŒŽ†App. 90-97.

  1. Y. Itoh, H. Sunami, and Y. Kamigaki, "Charge transfer efficiency in CCD," Oyo-butsuri, Vol. 41, No. 295, pp. 192-194, 1972.
  2. H. Sunami, "Introduction of overseas paper: CCD having buried channel under electrode gap," Proc. IEICE, Vol. 56. No. 10, pp. 1414-1415, October 1973.
  3. H. Sunami, "1981 Symposium on VLSI Technology," Proc. IEICE, Vol. 64, No. 12, p. 1289, December 1981.
  4. H. Sunami, "1983 IEEE International Solid-State Circuits Conference ('83 ISSCC)," Proc. IEICE, Vol. 66, No. 5, p. 459, May 1983.
  5. K. Ito and H. Sunami, "Design of memory cell to realize high-density dynamic RAM," Nikkei Electronics, pp. 169-193, July 3, 1983.
  6. H. Sunami, K. Ito, and S. Asai, "Megabit-class dynamic RAM teechnologies with cubic cell structure," Hitachi-hyoron, Vo. 66, p. 4, January 1984.
  7. H. Sunami, "IEDM '84," Proc. ITE, Vol. 39, No. 3, pp. 259-260A1985.
  8. N. Hashimoto, T. Masuhara, Hideo Sunami, T. Hagiwara, Y, Horiike, and S. Takasu, "0.2mm devices are forecated but UV lithography are not," Nikkei Microdevices, pp. 131-155, July 1985 (the initial issue).
  9. H. Sunami, "Mbit memory at 1985 IEDM," ULSI, pp. 33-36, March 1986”N.
  10. H. Sunami, "Report on the 18-th COnference on Solid-State Devices and Materials," SEMICON NEWS, Nobvember 1986 issue, pp. 82-87, 1986.
  11. H. Sunami, "Forecant of Greater Integration of DRAM," Science and Technology of Japan '86/Memory, pp. 39-45, 1986.
  12. H. Sunami and M. Nagata, "Limit of device integration," Oyo-bitsuri, Vol. 55, No. 4, pp. 349-353, 1986.
  13. H. Sunami, gThe State of the Art in Megabit Memory Technology : Critical Reviews of 4Mbit DRAM Technology, Cell Structures," JST Reports, Vol. 3, No. 1, pp. 21-26, Spring 1987.
  14. H. Sunami, "Forecant of 4M and 16M DRAMs-stack or trench," Monthly Semiconductor World, pp. 31-36, February 1988.
  15. H. Sunami, "16-Mbit DRAM, Electronics, pp. 30-34, 1988.
  16. Y. Kawamoto, T. Kure, T. Nishida, and H. Sunami, "Solutions in stack or trench and metallization with silicide and double Al layers," Nikke Microdevices, pp. 46-51, April 1988.
  17. H. Sunami, H. Kanbe, N. Susa, and H. Ishiwara, "Report on Conference on Solid-State Devices and Materials," Oyo-butsuri, Vo. 57, No. 11, pp. 1773-1775, 1988.
  18. H. Sunami, "Possibility of 1 Gbit Super LSI," Technology Forecant, Vol. 3, Japan Business Report Ltd., pp. 1-6A1989.
  19. H. Sunami, "Solutions with stack and trench," Nikke Microdevices, p. 48, May 1989.
  20. H. Sunami, "Sec. 4.2: Scaling of silicon devices," Reports on ULSI devices in 21st century (nanometer functional devices), pp. 37-42, Incorporated Foundation of Future Elecrtron Devices (FED), June 1989.
  21. H. Sunami, "Metallization of TiW, TiN, and Al-Si, and FLEX method as multi-layer lithography," Monthly Semiconductor WorldApp. 150-159, July 1989.
  22. H. Sunami, "Memory cell will change at 256M," Nikkei microdevices, pp. 134-135, August 1989.
  23. H. Sunami, E. noda, K. Tsumori, K. Chudan, K. Shida, M. Itoh, H. Tashiro, H. Kawanichi, A. Kawazu, H. Komuro, Y. Hosi, Mi, Suzuki, H. Nakanishi, Y. Kuroda, J. Yoshino, K. Ota, H. Shimada, and K. Ikezaki, Reports on the 37th Meeting of JSAP," Oyobutsuri, Vol. 59, No. 6, pp. 768-783, 1990.
  24. H. Sunami, To. Goto, K. Chudan, M. Haruna, R. Ito, Y. Ishida, G. Otsu, K. Takigawa, Y. Yasmazaki, M. Suzuki, H. Nakanishi, J. Matsunaga, K. Nakagawa, T. Murotani, K. Honma, T. Osawa, and Y. Kunitani, "the 51st Meeting of JSAP," Oyobutsuri, Vol. 60, No. 1, pp. 70-81, 1991.
  25. H. Sunami, "A hint of solar cell," Nikkei Microdevices, pp. 203-204, 1993.
  26. H. Sunami, "New scaling law at gigabit DRAM era," Nikkei Microdevices, pp. 112-123, December 1996.
  27. H. Sunami, "Book review: Science of semiconductor," Nikkei Microdevices, p. 25, June 1997.
  28. H. Sunami, "Overcome cell miniatuarizatiuon with new materials," Nikkei Microdevices, pp. 144-157, December 1997.
  29. H. Sunami and M. Suzuki, "Next generation integrated circuits and fabirication lien: Future scope and trend in 300-mm wafere line," Aerosol Research , Vol. 14, No. 1, pp. 11-18, 19999.
  30. H. Sunami, "Book review: Cemistry of semiconductor," Nikkei Microdevices, p. 25, June 1997.
  31. S. Yokoyama, K. Shibahara, A. Nkajima, T. Kikkawa, and H. Sunami, "Influence of oragnic gas contamination on hot-carrier immunity of thermal silicon dioxide," IEICE bulletin, Vol. SDM2001-47, pp. 19-24, 2001.
  32. H. Sunami, "Breakthrough to greater integration with new materials and new structures," Nikke Microdevices, pp. 90-97, March 2006.


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